`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/09/14 20:26:26
// Design Name: 
// Module Name: ID_EX
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module ID_EX(
    input   wire        rst,
    input   wire        clk,
    input   wire        nop,

    input   wire [31:0] i_rs_out,
    input   wire [31:0] i_rt_out,
    input   wire [31:0] i_inst_addr,
    input   wire [31:0] i_inst,
    
    output  wire [31:0] o_rs_out,
    output  wire [31:0] o_rt_out,
    output  wire [31:0] o_inst_addr,
    output  wire [31:0] o_inst,
    output  wire [31:0] o_imm32_zero,
    output  wire [31:0] o_imm32_sign
    
    );
    
    reg [31:0] t_rs_out;
    reg [31:0] t_rt_out;
    reg [31:0] t_inst_addr;
    reg [31:0] t_inst;
    reg [31:0] t_imm32_zero;
    reg [31:0] t_imm32_sign;
    
    assign o_rs_out = t_rs_out;
    assign o_rt_out = t_rt_out;
    assign o_inst_addr = t_inst_addr;
    assign o_inst = t_inst;
    assign o_imm32_zero = t_imm32_zero;
    assign o_imm32_sign = t_imm32_sign;
    
    always @(posedge clk) begin
        if (rst == 0 || nop) begin
            t_rs_out <= 0;
            t_rt_out <= 0;
            t_inst_addr <= 0;
            t_inst <= 0;
            t_imm32_zero <= 0;
            t_imm32_sign <= 0;
        end else begin
//            if (pause == 0) begin
                t_rs_out <= i_rs_out;
                t_rt_out <= i_rt_out;
                t_inst_addr <= i_inst_addr;
                t_inst <= i_inst;
                
                t_imm32_zero <= {16'h0000, i_inst[15:0]};
                t_imm32_sign <= i_inst[15] == 1 ? {16'hffff, i_inst[15:0]}
                    : {16'h0000, i_inst[15:0]};
//            end
        end
    end
endmodule
